All the gates used in the diagram represent NAND gates.

Thus, the output $Y$ can be calculated as follows

$\begin{array}{rcl}Y& =& \overline{\overline{A}·\overline{B}}\\ & =& \overline{\overline{A}}+\overline{\overline{B}}\\ & =& A+B\end{array}$

The above equation suggests that the output of the given combination yields the same result as an OR gate.

The truth table can be written as follows

$A$	$B$	$\overline{A}$	$\overline{B}$	$Y=\overline{\overline{A}·\overline{B}}$
$0$	$0$	$1$	$1$	$0$
$0$	$1$	$1$	$0$	$1$
$1$	$0$	$0$	$1$	$1$
$1$	$1$	$0$	$0$	$1$

Hence, this is the correct output.